ORACLESP-AK99999999 login: root
ORACLESP-AK99999999 login: root
Password:
Detecting screen size; please wait...done
Oracle(R) Integrated Lights Out Manager
Version 3.2.7.1.c r112301
Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
Warning: password is set to factory default.
Warning: HTTPS certificate is set to factory default.
Hostname: ORACLESP-AK99999999
->
->
-> show /SP/network
/SP/network
Targets:
interconnect
ipv6
test
Properties:
commitpending = (Cannot show property)
dhcp_clientid = none
dhcp_server_ip = none
ipaddress = 0.0.0.0
ipdiscovery = dhcp
ipgateway = 0.0.0.0
ipnetmask = 0.0.0.0
macaddress = 00:00:00:B3:00:10
managementport = MGMT
outofbandmacaddress = 00:00:00:B3:00:10
pendingipaddress = 0.0.0.0
pendingipdiscovery = dhcp
pendingipgateway = 0.0.0.0
pendingipnetmask = 0.0.0.0
pendingmanagementport = MGMT
pendingvlan_id = (none)
sidebandmacaddress = 00:00:00:B3:00:20
state = enabled
vlan_id = (none)
Commands:
cd
set
show
-> start /SYS
Are you sure you want to start /SYS (y/n)? Y
Starting /SYS
-> start /SP/console
Are you sure you want to start /SP/console (y/n)? y
Serial console started. To stop, type #.
@(#)Hostconfig 1.8.3.a 2016/09/16 14:15
2017-03-21 02:57:46 0:00:0> NOTICE: Firmware timezone is GMT
2017-03-21 02:57:47 0:00:0> NOTICE: Using HW change diag level and verbosity
2017-03-21 02:57:49 0:00:0> NOTICE: TPM is turned off
2017-03-21 02:57:52 0:00:0> NOTICE: Validating Configuration
2017-03-21 02:57:52 1:00:0> NOTICE: Available Strands: ffffffff.ffffffff
2017-03-21 02:57:52 0:00:0> NOTICE: Available Strands: ffffffff.ffffffff
2017-03-21 02:57:52 0:00:0> NOTICE: CPU Version: 003e004211030607
2017-03-21 02:57:52 1:00:0> NOTICE: CPU Version: 003e004211030607
2017-03-21 02:57:52 0:00:0> NOTICE: Enabled Strands: ffffffff.ffffffff
2017-03-21 02:57:53 1:00:0> NOTICE: Enabled Strands: ffffffff.ffffffff
2017-03-21 02:57:59 1:00:0> NOTICE: Active Strands: ffffffff.ffffffff
2017-03-21 02:57:59 0:00:0> NOTICE: Active Strands: ffffffff.ffffffff
2017-03-21 02:57:59 0:00:0> NOTICE: Starting Early POST
2017-03-21 02:58:05.080 1:0:0:0>RunEnv = HW
2017-03-21 02:58:05.229 0:0:0:0>RunEnv = HW
2017-03-21 02:58:09.315 0:0:0:0>POST 5.5.3.a 2016/08/26 13:52
Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
2017-03-21 02:58:09.430 0:0:0:0>SPARC-S7 Revision 1.1
2017-03-21 02:58:09.430 1:0:0:0>SPARC-S7 Revision 1.1
2017-03-21 02:58:09.511 0:0:0:0>Serial Number = 000c8cf0810b31c1
2017-03-21 02:58:09.551 1:0:0:0>Serial Number = 000c8cf0810af109
2017-03-21 02:58:10.591 0:0:0:0>Initial Globals: **** DiagLevel=Max, Phase=Early, Verbosity=Normal ****
2017-03-21 02:58:10.635 1:0:0:0>Initial Globals: **** DiagLevel=Max, Phase=Early, Verbosity=Normal ****
2017-03-21 02:58:10.704 0:0:0:0>POST Running.
2017-03-21 02:58:10.773 1:0:0:0>POST Running.
2017-03-21 02:58:10.792 0:0:0:0>Default RYOP
2017-03-21 02:58:10.835 1:0:0:0>Default RYOP
2017-03-21 02:58:12.844 0:0:0:0>Display Core Group Status
2017-03-21 02:58:12.880 1:0:0:0>Display Core Group Status
2017-03-21 02:58:12.915 0:0:0:0>Enabled 0000000000000003 Available 0000000000000003
2017-03-21 02:58:12.959 1:0:0:0>Enabled 0000000000000003 Available 0000000000000003
2017-03-21 02:58:13.221 0:0:0:0>COU L3 Register config for single POST download
2017-03-21 02:58:13.276 1:0:0:0>COU L3 Register config for single POST download
2017-03-21 02:58:13.725 0:0:0:0>L3Cache RAM tests from PROM
2017-03-21 02:58:13.777 1:0:0:0>L3Cache RAM tests from PROM
2017-03-21 02:58:28.401 0:0:0:0>L3Cache Hit verify test
2017-03-21 02:58:28.451 1:0:0:0>L3Cache Hit verify test
2017-03-21 02:58:28.886 0:0:0:0>L3Cache execution test
2017-03-21 02:58:28.933 1:0:0:0>L3Cache execution test
2017-03-21 02:58:29.554 0:0:0:0>L3Cache RAM tests
2017-03-21 02:58:29.598 1:0:0:0>L3Cache RAM tests
2017-03-21 02:58:47.304 0:0:0:0>L3Cache RAM tests of other SCCs
2017-03-21 02:58:47.366 1:0:0:0>L3Cache RAM tests of other SCCs
2017-03-21 02:59:04.869 0:0:0:0>Run from Cache
2017-03-21 02:59:04.948 1:0:0:0>Run from Cache
2017-03-21 02:59:09.708 0:0:0:0>Setup Multithread Cache Environment
2017-03-21 02:59:09.763 1:0:0:0>Setup Multithread Cache Environment
2017-03-21 02:59:13.302 0:0:0:0>L2ICache RAM tests
2017-03-21 02:59:13.359 1:0:0:0>L2ICache RAM tests
2017-03-21 02:59:14.653 0:0:0:0>L2Cache execution test
2017-03-21 02:59:14.679 0:0:0:0>L2D0Cache RAM tests
2017-03-21 02:59:14.710 1:0:0:0>L2Cache execution test
2017-03-21 02:59:14.737 1:0:0:0>L2D0Cache RAM tests
2017-03-21 02:59:15.956 0:0:0:0>L2D1Cache RAM tests
2017-03-21 02:59:16.014 1:0:0:0>L2D1Cache RAM tests
2017-03-21 02:59:17.233 0:0:0:0>L2Cache Hit verify test
2017-03-21 02:59:17.260 0:0:0:0>DCache Inits from PROM
2017-03-21 02:59:17.292 1:0:0:0>L2Cache Hit verify test
2017-03-21 02:59:17.319 1:0:0:0>DCache Inits from PROM
2017-03-21 02:59:19.299 0:0:0:0>DCache RAM tests from PROM
2017-03-21 02:59:21.366 1:0:0:0>DCache RAM tests from PROM
2017-03-21 02:59:26.380 0:0:0:0>DCache Tags tests from PROM
2017-03-21 02:59:28.453 1:0:0:0>DCache Tags tests from PROM
2017-03-21 02:59:33.443 0:0:0:0>DCache Inits from PROM
2017-03-21 02:59:34.479 0:0:0:0>ICache Inits from PROM
2017-03-21 02:59:35.521 0:0:0:0>ICache RAM tests from PROM
2017-03-21 02:59:35.525 1:0:0:0>DCache Inits from PROM
2017-03-21 02:59:39.579 1:0:0:0>ICache Inits from PROM
2017-03-21 02:59:39.613 1:0:0:0>ICache RAM tests from PROM
2017-03-21 02:59:42.627 0:0:0:0>ICache Tags tests from PROM
2017-03-21 02:59:46.724 1:0:0:0>ICache Tags tests from PROM
2017-03-21 02:59:49.689 0:0:0:0>ICache Inits from PROM
2017-03-21 02:59:49.714 0:0:0:0>cache_park_threads
2017-03-21 02:59:50.434 0:0:0:0>L3Cache Flush of Other SCCs
2017-03-21 02:59:50.562 0:0:0:0>Setup CPU MBISI
2017-03-21 02:59:50.577 0:0:0:0>Sync Chips
2017-03-21 02:59:53.787 1:0:0:0>ICache Inits from PROM
2017-03-21 02:59:54.816 1:0:0:0>cache_park_threads
2017-03-21 02:59:55.536 1:0:0:0>L3Cache Flush of Other SCCs
2017-03-21 02:59:55.664 1:0:0:0>Setup CPU MBISI
2017-03-21 02:59:55.679 1:0:0:0>Sync Chips
2017-03-21 02:59:55.692 1:0:0:0>POST return to PROM
2017-03-21 02:59:55.875 1:0:0:0>L3Cache Final Flush
2017-03-21 02:59:56.187 1:0:0:0>POST Phase Complete
2017-03-21 02:59:56.241 1:0:0:0>POST Complete. Return back to HC PC: 0x0003fffff0282820 SP: 0x0003fffff2e44521
2017-03-21 02:59:56.615 0:0:0:0>POST return to PROM
2017-03-21 02:59:56.843 0:0:0:0>L3Cache Final Flush
2017-03-21 02:59:57.231 0:0:0:0>POST Phase Complete
2017-03-21 02:59:57.301 0:0:0:0>POST Complete. Return back to HC PC: 0x0003fffff0282820 SP: 0x0003fffff2e44521
2017-03-21 02:59:58.407 0:0:0:0>POST Exit reason = 0
2017-03-21 03:00:01 0:00:0> NOTICE: Active Strands: ffffffff.ffffffff
2017-03-21 03:00:01 1:00:0> NOTICE: Active Strands: ffffffff.ffffffff
2017-03-21 03:00:27 0:00:0> NOTICE: Pretraining Coherency Links (1 of 3)
2017-03-21 03:00:30 0:00:0> NOTICE: Pretraining Coherency Links (2 of 3)
2017-03-21 03:01:01 0:00:0> NOTICE: Pretraining Coherency Links (3 of 3)
2017-03-21 03:01:19 0:00:0> NOTICE: Training Coherency Links
2017-03-21 03:01:25 1:00:0> NOTICE: Configuring Caches
2017-03-21 03:01:25 0:00:0> NOTICE: Configuring Caches
2017-03-21 03:01:25 0:00:0> NOTICE: Enabling fatal error detection
2017-03-21 03:01:25 0:00:0> NOTICE: Starting System POST
2017-03-21 03:01:31.421 1:0:0:0>RunEnv = HW
2017-03-21 03:01:31.568 0:0:0:0>RunEnv = HW
2017-03-21 03:01:36.635 1:0:0:0>Initial Globals: **** DiagLevel=Max, Phase=System, Verbosity=Normal ****
2017-03-21 03:01:36.656 0:0:0:0>Initial Globals: **** DiagLevel=Max, Phase=System, Verbosity=Normal ****
2017-03-21 03:01:36.749 1:0:0:0>POST Running.
2017-03-21 03:01:36.818 0:0:0:0>POST Running.
2017-03-21 03:01:36.836 1:0:0:0>Default RYOP
2017-03-21 03:01:36.881 0:0:0:0>Default RYOP
2017-03-21 03:01:48.279 1:0:0:0>Display Core Group Status
2017-03-21 03:01:48.316 0:0:0:0>Display Core Group Status
2017-03-21 03:01:48.350 1:0:0:0>Enabled 0000000000000003 Available 0000000000000003
2017-03-21 03:01:48.393 0:0:0:0>Enabled 0000000000000003 Available 0000000000000003
2017-03-21 03:01:48.737 1:0:0:0>Disable MCU Error Check
2017-03-21 03:01:48.797 0:0:0:0>Disable MCU Error Check
2017-03-21 03:01:49.002 1:0:0:0>Disable All L3 Cache Errors
2017-03-21 03:01:49.065 0:0:0:0>Disable All L3 Cache Errors
2017-03-21 03:01:49.372 1:0:0:0>MCU csr write, read, verify test
2017-03-21 03:01:49.438 0:0:0:0>MCU csr write, read, verify test
2017-03-21 03:01:49.642 1:0:0:0>Probe Memory
2017-03-21 03:01:49.711 0:0:0:0>Probe Memory
2017-03-21 03:01:49.751 1:0:0:0>Total Node Memory Size: 128GB
2017-03-21 03:01:49.820 0:0:0:0>Total Node Memory Size: 128GB
2017-03-21 03:01:50.514 1:0:0:0>Memory BIST Extension 1
2017-03-21 03:01:50.583 1:0:0:0>MemBIST Full Parallel:
2017-03-21 03:01:50.584 0:0:0:0>Memory BIST Extension 1
2017-03-21 03:01:50.696 0:0:0:0>MemBIST Full Parallel:
2017-03-21 03:02:50.649 1:0:0:0>Transfer DIMM Control to HOST Test
2017-03-21 03:02:50.757 0:0:0:0>Transfer DIMM Control to HOST Test
2017-03-21 03:02:50.955 1:0:0:0>Idle and Sync CMP Masters
2017-03-21 03:02:51.065 0:0:0:0>Idle and Sync CMP Masters
2017-03-21 03:02:51.342 0:0:0:0>Initial memory scrub
2017-03-21 03:02:52.079 0:0:0:0>POST Critical region memory check
2017-03-21 03:02:53.279 0:0:0:0>Copy POST to DRAM
2017-03-21 03:03:08.166 0:0:0:0>Jump to DRAM
2017-03-21 03:03:09.922 0:0:0:0>Setup Multi Thread Environment
2017-03-21 03:03:09.984 0:0:0:0>Wake CMP Masters
2017-03-21 03:03:10.200 0:0:0:0>Set CMP Masters Present
2017-03-21 03:03:10.229 0:0:0:0>Fill Memory Chunks
2017-03-21 03:03:10.445 0:0:0:0>Setup CPU Present
2017-03-21 03:03:10.668 0:0:0:0>Wake CMP Threads
2017-03-21 03:03:11.547 0:0:0:0>Enable SSI Fetch Remap
2017-03-21 03:03:11.768 0:0:0:0>Set CMP Threads Present
2017-03-21 03:03:11.797 0:0:0:0>Disable CPU Core Errors
2017-03-21 03:03:12.023 0:0:0:0>Disable Core Hang Detection
2017-03-21 03:03:12.250 0:0:0:0>Disable All L2I Cache Errors
2017-03-21 03:03:12.670 0:0:0:0>Disable All L2D0 Cache Errors
2017-03-21 03:03:13.091 0:0:0:0>Disable All L2D1 Cache Errors
2017-03-21 03:03:13.511 0:0:0:0>Disable All L3 Cache Errors
2017-03-21 03:03:13.931 0:0:0:0>Dump Dimm Size
/SYS/MB/CMP0/MCU0/CH0/D0 0x0000000400000000
/SYS/MB/CMP0/MCU0/CH0/D1 0x0000000400000000
/SYS/MB/CMP0/MCU0/CH1/D0 0x0000000400000000
/SYS/MB/CMP0/MCU0/CH1/D1 0x0000000400000000
/SYS/MB/CMP0/MCU1/CH0/D0 0x0000000400000000
/SYS/MB/CMP0/MCU1/CH0/D1 0x0000000400000000
/SYS/MB/CMP0/MCU1/CH1/D0 0x0000000400000000
/SYS/MB/CMP0/MCU1/CH1/D1 0x0000000400000000
/SYS/MB/CMP1/MCU0/CH0/D0 0x0000000400000000
/SYS/MB/CMP1/MCU0/CH0/D1 0x0000000400000000
/SYS/MB/CMP1/MCU0/CH1/D0 0x0000000400000000
/SYS/MB/CMP1/MCU0/CH1/D1 0x0000000400000000
/SYS/MB/CMP1/MCU1/CH0/D0 0x0000000400000000
/SYS/MB/CMP1/MCU1/CH0/D1 0x0000000400000000
/SYS/MB/CMP1/MCU1/CH1/D0 0x0000000400000000
/SYS/MB/CMP1/MCU1/CH1/D1 0x0000000400000000
2017-03-21 03:03:14.215 0:0:0:0>Memory Clear
2017-03-21 03:03:26.782 0:0:0:0>Memory ND Scan
2017-03-21 03:03:39.976 0:0:0:0>Flush L3 cache
2017-03-21 03:03:40.290 0:0:0:0>Get scvar thresholds
2017-03-21 03:03:40.364 0:0:0:0>Set Global Error Steering
2017-03-21 03:03:40.582 0:0:0:0>Enable CPU Core Errors
2017-03-21 03:03:40.808 0:0:0:0>Enable CPU Strand Error Traps
2017-03-21 03:03:41.102 0:0:0:0>Enable COU Errors
2017-03-21 03:03:41.322 0:0:0:0>Enable MCU Errors
2017-03-21 03:03:41.543 0:0:0:0>Enable L2I Cache Errors
2017-03-21 03:03:41.964 0:0:0:0>Enable L2D0 Cache Errors
2017-03-21 03:03:42.383 0:0:0:0>Enable L2D1 Cache Errors
2017-03-21 03:03:42.803 0:0:0:0>Enable L3 Cache Errors
2017-03-21 03:03:43.223 0:0:0:0>Enable All Coherency Link Errors
2017-03-21 03:03:43.453 0:0:0:0>Save DVFS information
2017-03-21 03:03:43.479 0:0:0:0>CPU SOC Stick Test
2017-03-21 03:03:44.701 0:0:0:0>CPU Core Stick Test
2017-03-21 03:03:49.536 0:0:0:0>CPU Tick Counter Test
2017-03-21 03:03:50.765 0:0:0:0>Verify CPU Frequency
2017-03-21 03:03:53.191 0:0:0:0>Save Restore Test
2017-03-21 03:03:53.499 0:0:0:0>SPARC Atomic Instructions Test
2017-03-21 03:03:53.789 0:0:0:0>Memory ND Scan
2017-03-21 03:04:06.872 0:0:0:0>Adjust Memory Chunks
2017-03-21 03:04:07.120 0:0:0:0>Initialize Memory for TSB
2017-03-21 03:04:07.190 0:0:0:0>Virtual Memory Setup
2017-03-21 03:04:07.201 0:0:0:0>virtual_mem_setup: pa->ra 1 cmp=0x0, nps=0000000000000000
2017-03-21 03:04:07.217 0:0:0:0>virtual_mem_setup: pa->ra 2 cmp=0x0, gmbe=0000000000c6a1c0
2017-03-21 03:04:07.234 0:0:0:0>CMP 0 start-ra = 0000000000c6a1c0 end-ra 0000002000000000
2017-03-21 03:04:07.250 0:0:0:0>Total sys Mem = 0000002000000000
2017-03-21 03:04:07.358 1:0:0:0>virtual_mem_setup: pa->ra 1 cmp=0x1, nps=0000400000000000
2017-03-21 03:04:07.374 1:0:0:0>CMP 1 start-ra = 0000002000000000 end-ra 0000004000000000
2017-03-21 03:04:07.390 1:0:0:0>Total sys Mem = 0000004000000000
2017-03-21 03:04:07.471 0:0:0:0>CPU Startup
2017-03-21 03:04:07.757 0:0:0:0>DAX init
2017-03-21 03:04:07.983 0:0:0:0>Enable DAX Errors
2017-03-21 03:04:08.211 0:0:0:0>IO PCIe Configuration Space Register Test
2017-03-21 03:04:08.522 0:0:0:0>IO PCIe Memory Space Register Test
2017-03-21 03:04:08.910 0:0:0:0>Read MBOM and DBP type
2017-03-21 03:04:09.232 0:0:0:0>Alloc Tunables
2017-03-21 03:04:09.392 0:0:0:0>HB PCIE LINK ENABLE
2017-03-21 03:04:19.955 0:0:0:0>PCI PROBE
2017-03-21 03:04:36.236 0:0:0:0>SIBS LINK CONFIGURATION
2017-03-21 03:04:36.483 0:0:0:0>Free Tunables
2017-03-21 03:04:36.516 0:0:0:0>Verify Memory Access
2017-03-21 03:05:14.860 0:0:0:0>Memory Address Ascending Test
2017-03-21 03:05:44.172 0:0:0:0>Memory Address Descending Test
2017-03-21 03:06:12.426 0:0:0:0>Memory Masest Test
2017-03-21 03:07:59.495 0:0:0:0>Burn In with FGU N Memory Access
2017-03-21 03:08:38.664 0:0:0:0>Memory Set 64
2017-03-21 03:08:48.688 0:0:0:0>ICache Tag Parity Functional Test
2017-03-21 03:09:01.601 0:0:0:0>DCache Parity Functional Test
2017-03-21 03:09:14.513 0:0:0:0>DCache Tag Parity Functional Test
2017-03-21 03:09:27.425 0:0:0:0>L3Cache Flush verify test
2017-03-21 03:09:27.654 0:0:0:0>L3Cache Hash Logic Verify test
2017-03-21 03:09:28.140 0:0:0:0>Disable All L2D1 Cache Errors
2017-03-21 03:09:28.568 0:0:0:0>Disable All L2D0 Cache Errors
2017-03-21 03:09:28.999 0:0:0:0>L3Cache Data Data ECC test
2017-03-21 03:09:29.515 0:0:0:0>Enable L2D1 Cache Errors
2017-03-21 03:09:29.942 0:0:0:0>Enable L2D0 Cache Errors
2017-03-21 03:09:30.380 0:0:0:0>Enable Overlap Operation
2017-03-21 03:09:32.027 0:0:0:0>L2/L3Cache Line Fill Stress Test
2017-03-21 03:09:35.731 0:0:0:0>L3Cache Thrashing Test
2017-03-21 03:09:48.469 0:0:0:0>System Data Consistency Test
2017-03-21 03:09:49.614 0:0:0:0>DRAM ECC test
2017-03-21 03:09:55.674 0:0:0:0>Graphics Instructions Test
2017-03-21 03:09:55.910 0:0:0:0>Graphics Functional Test
2017-03-21 03:09:56.201 0:0:0:0>Enable Floating Point Unit Test
2017-03-21 03:09:56.500 0:0:0:0>FPU Move Register Test
2017-03-21 03:09:56.799 0:0:0:0>FPU Register to Memory Test
2017-03-21 03:09:57.098 0:0:0:0>FPU Add Test
2017-03-21 03:09:57.334 0:0:0:0>FPU Subtract Test
2017-03-21 03:09:57.569 0:0:0:0>FPU Multiply Test
2017-03-21 03:09:57.805 0:0:0:0>FPU Divide Test
2017-03-21 03:09:58.040 0:0:0:0>FPU Sqrt Test
2017-03-21 03:09:58.275 0:0:0:0>FPU Branch Test
2017-03-21 03:09:59.473 0:0:0:0>FPU Combined Test
2017-03-21 03:10:07.203 0:0:0:0>FPU Memory Test
2017-03-21 03:10:41.659 0:0:0:0>FPU Stress Test
2017-03-21 03:11:06.551 0:0:0:0>MMU ITLB RAM Test
2017-03-21 03:11:06.786 0:0:0:0>MMU DTLB RAM Test
2017-03-21 03:11:07.022 0:0:0:0>MMU RA2PAC RAM Test
2017-03-21 03:11:07.256 0:0:0:0>MMU Register Test
2017-03-21 03:11:07.558 0:0:0:0>MMU Per Core Initialization
2017-03-21 03:11:07.796 0:0:0:0>MMU Per Strand Initialization
2017-03-21 03:11:08.091 0:0:0:0>IMMU TLB Demap All Test
2017-03-21 03:11:08.389 0:0:0:0>IMMU TLB Demap Page Test
2017-03-21 03:11:08.687 0:0:0:0>IMMU TLB Demap Context Test
2017-03-21 03:11:08.925 0:0:0:0>IMMU TLB Demap All Pages Test
2017-03-21 03:11:09.163 0:0:0:0>DMMU TLB Demap All Test
2017-03-21 03:11:09.466 0:0:0:0>DMMU TLB Demap Page Test
2017-03-21 03:11:09.768 0:0:0:0>DMMU TLB Demap Context Test
2017-03-21 03:11:10.006 0:0:0:0>DMMU TLB Demap All Pages Test
2017-03-21 03:11:10.243 0:0:0:0>IMMU Illegal Instruction Trap
2017-03-21 03:11:10.580 0:0:0:0>IMMU Fast Ins Translation Miss Trap
2017-03-21 03:11:10.908 0:0:0:0>DMMU Real Data Translation Miss Trap
2017-03-21 03:11:11.228 0:0:0:0>DMMU Fast Data Translation Miss Trap
2017-03-21 03:11:11.553 0:0:0:0>DMMU Fast Access Protection Trap
2017-03-21 03:11:11.885 0:0:0:0>DMMU DAE Priv Violation Trap
2017-03-21 03:11:12.214 0:0:0:0>DMMU Verify Page Sizes Test
2017-03-21 03:11:12.602 0:0:0:0>IMMU Verify Page Sizes Test
2017-03-21 03:11:12.965 0:0:0:0>IMMU TLB CAM Parity test
2017-03-21 03:11:13.196 0:0:0:0>IMMU TLB Data Parity test
2017-03-21 03:11:13.426 0:0:0:0>DMMU TLB CAM Parity test
2017-03-21 03:11:13.656 0:0:0:0>DMMU TLB Data Parity test
2017-03-21 03:11:13.885 0:0:0:0>MMU Register Array Parity Test
2017-03-21 03:11:14.127 0:0:0:0>MMU TSB Test
2017-03-21 03:11:14.393 0:0:0:0>MMU Degraded Page Size Test
2017-03-21 03:11:14.642 0:0:0:0>MMU Write Bit Masking Test
2017-03-21 03:11:15.051 0:0:0:0>MMU PA to PA Translation Test
2017-03-21 03:11:15.290 0:0:0:0>MMU VA Masking Test
2017-03-21 03:11:15.555 0:0:0:0>MMU ADI Test
2017-03-21 03:11:20.607 0:0:0:0>MMU Per Core Initialization
2017-03-21 03:11:20.845 0:0:0:0>MMU Per Strand Initialization
2017-03-21 03:11:21.147 0:0:0:0>SPU Crypto MPMUL
2017-03-21 03:11:23.418 0:0:0:0>SPU Crypto SHA 512
2017-03-21 03:11:25.688 0:0:0:0>SPU Crypto MD5
2017-03-21 03:11:27.962 0:0:0:0>SPU Crypto MONTMUL
2017-03-21 03:11:30.235 0:0:0:0>SPU Crypto SHA 1
2017-03-21 03:11:32.509 0:0:0:0>SPU Crypto MONTSQR
2017-03-21 03:11:34.783 0:0:0:0>SPU Crypto SHA 256
2017-03-21 03:11:37.056 0:0:0:0>SPU Crypto CRC32 1008
2017-03-21 03:11:39.327 0:0:0:0>SPU Crypto AES 128 Encrypt
2017-03-21 03:11:41.601 0:0:0:0>SPU Crypto AES 256 Key Decrypt
2017-03-21 03:11:43.877 0:0:0:0>SPU Crypto DES 1 Key Encrypt
2017-03-21 03:11:46.149 0:0:0:0>SPU Camellia 128 Encrypt
2017-03-21 03:11:48.424 0:0:0:0>SPU Crypto XMONTMUL
2017-03-21 03:11:50.697 0:0:0:0>SPU Crypto XMONTSQR
2017-03-21 03:11:52.968 0:0:0:0>SPU Crypto XMPMUL
2017-03-21 03:11:55.237 0:0:0:0>CPU XCALL Strand Level Test
2017-03-21 03:11:55.614 0:0:0:0>CPU XCALL Chip Level Test
2017-03-21 03:11:55.980 0:0:0:0>CPU XCALL DCU Level Test
2017-03-21 03:11:56.174 0:0:0:0>CPU XCALL Inter DCU or System Level Test
2017-03-21 03:11:56.848 0:0:0:0>CPU MONDO Strand Level Test
2017-03-21 03:11:57.154 0:0:0:0>DEV MONDO Strand Level Test
2017-03-21 03:11:57.459 0:0:0:0>Resumable Error Strand Level Test
2017-03-21 03:11:57.760 0:0:0:0>Non Resumable Error Strand Level Test
2017-03-21 03:11:58.065 0:0:0:0>Allocated TSBs
2017-03-21 03:12:00.063 0:0:0:0>Setup the Global TSB
2017-03-21 03:12:00.086 0:0:0:0>Setup Supervisor mode
2017-03-21 03:12:00.376 0:0:0:0>Block Memory Test
2017-03-21 03:12:00.451 0:0:0:0>. . . . . . . . .
2017-03-21 03:12:57.907 0:0:0:0>Cross Node Block Memory Test
2017-03-21 03:12:58.053 0:0:0:0>. . . . . . . . .
2017-03-21 03:14:19.115 0:0:0:0>DAX Queues Test
2017-03-21 03:14:19.420 0:0:0:0>DAX Function Test Setup
2017-03-21 03:14:19.493 0:0:0:0>DAX Functional Test
2017-03-21 03:14:22.478 0:0:0:0>DVFS HW Temp Sensor Test
2017-03-21 03:14:22.577 0:0:0:0>Display PCI Probed
2017-03-21 03:14:22.613 0:0:0:0>Probed PCI devices
N:IL:P | NAC | Address | BDF | VID | DID |RID | SSID | SVID |Wth Spd
0:0:0 | /SYS/MB/PCIE_SWITCH0/PCIE_LINK0 | 2007c00100000 | 01:00:0 | 111d | 80ba | 03 | 0000 | 0000 | 8 G3
0:0:0 | /SYS/MB/PCIE_SWITCH0/PCIE_LINK1 | 2007c00208000 | 02:01:0 | 111d | 80ba | 03 | 0000 | 0000 | 8 G3
0:0:0 | /SYS/MB/NET0 | 2007c00300000 | 03:00:0 | 8086 | 1589 | 02 | 7b1e | 108e | 8 G3
0:0:0 | /SYS/MB/NET1 | 2007c00301000 | 03:00:1 | 8086 | 1589 | 02 | 0000 | 108e | 8 G3
0:0:0 | /SYS/MB/NET2 | 2007c00302000 | 03:00:2 | 8086 | 1589 | 02 | 0000 | 108e | 8 G3
0:0:0 | /SYS/MB/NET3 | 2007c00303000 | 03:00:3 | 8086 | 1589 | 02 | 0000 | 108e | 8 G3
0:0:0 | /SYS/MB/PCIE_SWITCH0/PCIE_LINK2 | 2007c00210000 | 02:02:0 | 111d | 80ba | 03 | 0000 | 0000 | 1 G2
0:0:0 | /SYS/MB/USB_CTRL | 2007c00400000 | 04:00:0 | 104c | 8241 | 02 | 0000 | 0000 | 1 G2
0:0:0 | /SYS/MB/PCIE_SWITCH1/PCIE_LINK0 | 2007c00500000 | 05:00:0 | 111d | 80ba | 03 | 0000 | 0000 | 8 G3
0:0:0 | /SYS/MB/PCIE_SWITCH1/PCIE_LINK4 | 2007c00620000 | 06:04:0 | 111d | 80ba | 03 | 4268 | 108e | 0 G1
0:0:0 | /SYS/MB/PCIE_SWITCH1/PCIE_LINK5 | 2007c00628000 | 06:05:0 | 111d | 80ba | 03 | 4268 | 108e | 0 G1
0:0:0 | /SYS/MB/PCIE_SWITCH1/PCIE_LINK13 | 2007c00698000 | 06:19:0 | 111d | 80ba | 03 | 0000 | 0000 | 0 G1
1:0:0 | /SYS/MB/PCIE_SWITCH0/PCIE_LINK0 | 2027c00a00000 | 10:00:0 | 111d | 80ba | 03 | 0000 | 0000 | 8 G3
1:0:0 | /SYS/MB/PCIE_SWITCH0/PCIE_LINK11 | 2027c00b88000 | 11:17:0 | 111d | 80ba | 03 | 0000 | 0000 | 4 G3
1:0:0 | /SYS/MB/RISER1/PCIE1 | 2027c00c00000 | 12:00:0 | 1077 | 2031 | 02 | 024d | 1077 | 4 G3
1:0:0 | /SYS/MB/RISER1/PCIE1 | 2027c00c01000 | 12:00:1 | 1077 | 2031 | 02 | 024d | 1077 | 4 G3
1:0:0 | /SYS/MB/PCIE_SWITCH0/PCIE_LINK12 | 2027c00b90000 | 11:18:0 | 111d | 80ba | 03 | 0000 | 0000 | 0 G1
1:0:0 | /SYS/MB/PCIE_SWITCH1/PCIE_LINK0 | 2027c00e00000 | 14:00:0 | 111d | 80ba | 03 | 0000 | 0000 | 8 G3
1:0:0 | /SYS/MB/PCIE_SWITCH1/PCIE_LINK6 | 2027c00f30000 | 15:06:0 | 111d | 80ba | 03 | 4268 | 108e | 0 G1
1:0:0 | /SYS/MB/PCIE_SWITCH1/PCIE_LINK7 | 2027c00f38000 | 15:07:0 | 111d | 80ba | 03 | 4268 | 108e | 0 G1
1:0:0 | /SYS/MB/PCIE_SWITCH1/PCIE_LINK14 | 2027c00fa0000 | 15:20:0 | 111d | 80ba | 03 | 0000 | 0000 | 8 G3
1:0:0 | /SYS/MB/RISER3/PCIE4 | 2027c01200000 | 18:00:0 | 1000 | 0097 | 02 | 30e0 | 1000 | 8 G3
2017-03-21 03:14:23.131 0:0:0:0>Setup LE TSB Page
2017-03-21 03:14:23.198 0:0:0:0>CHECK PCI TOPOLOGY
2017-03-21 03:14:23.240 0:0:0:0> NAC VID DID Width Speed Status
2017-03-21 03:14:23.259 0:0:0:0>-----------------------------------------------------------------------------
2017-03-21 03:14:23.278 0:0:0:0> /SYS/MB/CMP0/IOS0/RP0/PCIE_LINK 108e b008 8 G3 Clean
2017-03-21 03:14:23.298 0:0:0:0> /SYS/MB/PCIE_SWITCH0/PCIE_LINK0 111d 80ba 8 G3 Clean
2017-03-21 03:14:23.318 0:0:0:0> /SYS/MB/PCIE_SWITCH0/PCIE_LINK1 111d 80ba 8 G3 Clean
2017-03-21 03:14:23.338 0:0:0:0> /SYS/MB/NET0 8086 1589 8 G3 Clean
2017-03-21 03:14:23.357 0:0:0:0> /SYS/MB/NET1 8086 1589 8 G3 Clean
2017-03-21 03:14:23.377 0:0:0:0> /SYS/MB/NET2 8086 1589 8 G3 Clean
2017-03-21 03:14:23.397 0:0:0:0> /SYS/MB/NET3 8086 1589 8 G3 Clean
2017-03-21 03:14:23.416 0:0:0:0> /SYS/MB/PCIE_SWITCH0/PCIE_LINK2 111d 80ba 1 G2 Clean
2017-03-21 03:14:23.436 0:0:0:0> /SYS/MB/USB_CTRL 104c 8241 1 G2 Clean
2017-03-21 03:14:23.456 0:0:0:0> /SYS/MB/CMP0/IOS0/RP1/PCIE_LINK 108e b008 8 G3 Clean
2017-03-21 03:14:23.476 0:0:0:0> /SYS/MB/PCIE_SWITCH1/PCIE_LINK0 111d 80ba 8 G3 Clean
2017-03-21 03:14:23.495 0:0:0:0> /SYS/MB/PCIE_SWITCH1/PCIE_LINK4 111d 80ba 0 G1 Clean
2017-03-21 03:14:23.515 0:0:0:0> /SYS/DBP/NVME0 ------------------------------
2017-03-21 03:14:23.535 0:0:0:0> /SYS/MB/PCIE_SWITCH1/PCIE_LINK5 111d 80ba 0 G1 Clean
2017-03-21 03:14:23.554 0:0:0:0> /SYS/DBP/NVME1 ------------------------------
2017-03-21 03:14:23.574 0:0:0:0> /SYS/MB/PCIE_SWITCH1/PCIE_LINK13 111d 80ba 0 G1 Clean
2017-03-21 03:14:23.594 0:0:0:0> /SYS/MB/RISER3/PCIE3 ------------------------------
2017-03-21 03:14:23.614 0:0:0:0> /SYS/MB/CMP1/IOS0/RP0/PCIE_LINK 108e b008 8 G3 Clean
2017-03-21 03:14:23.633 0:0:0:0> /SYS/MB/PCIE_SWITCH0/PCIE_LINK0 111d 80ba 8 G3 Clean
2017-03-21 03:14:23.653 0:0:0:0> /SYS/MB/PCIE_SWITCH0/PCIE_LINK11 111d 80ba 4 G3 Clean
2017-03-21 03:14:23.673 0:0:0:0> /SYS/MB/RISER1/PCIE1 1077 2031 4 G3 Clean
2017-03-21 03:14:23.692 0:0:0:0> /SYS/MB/RISER1/PCIE1 1077 2031 4 G3 Clean
2017-03-21 03:14:23.712 0:0:0:0> /SYS/MB/PCIE_SWITCH0/PCIE_LINK12 111d 80ba 0 G1 Clean
2017-03-21 03:14:23.732 0:0:0:0> /SYS/MB/RISER2/PCIE2 ------------------------------
2017-03-21 03:14:23.752 0:0:0:0> /SYS/MB/CMP1/IOS0/RP1/PCIE_LINK 108e b008 8 G3 Clean
2017-03-21 03:14:23.772 0:0:0:0> /SYS/MB/PCIE_SWITCH1/PCIE_LINK0 111d 80ba 8 G3 Clean
2017-03-21 03:14:23.791 0:0:0:0> /SYS/MB/PCIE_SWITCH1/PCIE_LINK6 111d 80ba 0 G1 Clean
2017-03-21 03:14:23.811 0:0:0:0> /SYS/DBP/NVME2 ------------------------------
2017-03-21 03:14:23.831 0:0:0:0> /SYS/MB/PCIE_SWITCH1/PCIE_LINK7 111d 80ba 0 G1 Clean
2017-03-21 03:14:23.850 0:0:0:0> /SYS/DBP/NVME3 ------------------------------
2017-03-21 03:14:23.870 0:0:0:0> /SYS/MB/PCIE_SWITCH1/PCIE_LINK14 111d 80ba 8 G3 Clean
System Configuration Tool
System Configuration Tool enables you to specify the following
configuration parameters for your newly-installed Oracle Solaris 11
system:
- system hostname, network, time zone and locale, date and time, user
and root accounts, name services, keyboard layout, support
System Configuration Tool produces an SMF profile file in
/etc/svc/profile/sysconfig/sysconfig-20170321-031725.
How to navigate through this tool:
- Use the function keys listed at the bottom of each screen to move
from screen to screen and to perform other operations.
- Use the up/down arrow keys to change the selection or to move
between input fields.
- If your keyboard does not have function keys, or they do not
respond, press ESC; the legend at the bottom of the screen will
change to show the ESC keys for navigation and other functions.
F2_Continue F6_Help F9_Quit
Serial console stopped.
->
-> show /SYS
/SYS
Targets:
DBP
FAN_FAULT
INTSW
LOCATE
MB
OK
PS0
PS1<
